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| ltc2242-10 1 224210fd typical a pplica t ion fea t ures a pplica t ions descrip t ion 10-bit, 250msps adc the ltc ? 2242-10 is a 250msps, sampling 10-bit a/d con- verter designed for digitizing high frequency, wide dynamic range signals. the ltc2240-10 is perfect for demanding communications applications with ac performance that includes 60.5db snr and 78db sfdr. ultralow jitter of 95fs rms allows if undersampling with excellent noise performance. dc specs include 0.4lsb inl (typ), 0.2lsb dnl (typ) and no missing codes over temperature. the digital outputs can be either differential lvds, or single-ended cmos. there are three format options for the cmos outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate with either interleaved or simultaneous update. a separate output power supply allows the cmos output swing to range from 0.5v to 2.625v. the enc + and enc C inputs may be driven differentially or single ended with a sine wave, pecl, lvds, ttl, or cmos inputs. an optional clock duty cycle stabilizer allows high performance over a wide range of clock duty cycles. sfdr vs input frequency n sample rate: 250msps n 60.5db snr n 78db sfdr n 1.2ghz full power bandwidth s/h n single 2.5v supply n low power dissipation: 740mw n lvds, cmos, or demultiplexed cmos outputs n selectable input ranges: 0.5v or 1v n no missing codes n optional clock duty cycle stabilizer n shutdown and nap modes n data ready output clock n pin compatible family 250msps: ltc2242-12 (12-bit), l tc2242-10 (10-bit) 210msps: ltc2241-12 (12-bit), l tc2241-10 (10-bit) 170msps: ltc2240-12 (12-bit), l tc2240-10 (10-bit) 185msps: ltc2220-1 (12-bit)* 170msps: ltc2220 (12-bit), l tc2230 (10-bit)* 135msps: ltc2221 (12-bit), l tc2231 (10-bit)* n 64-pin 9mm 9mm qfn package n wireless and wired broadband communication n cable head-end systems n power amplifier linearization n communications test equipment l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. *ltc2220-1, ltc2220, ltc2221, ltc2230, ltc2231 are 3.3v parts. ? + input s/h correction logic output drivers 10-bit pipelined adc core clock/duty cycle control flexible reference d9 ? ? ? d0 encode input refh refl analog input 224210 ta01 cmos or lvds 0.5v to 2.625v 2.5v v dd ov dd ognd input frequency (mhz) 0 sfdr (dbfs) 70 80 85 800 224210 g11 60 50 65 75 55 45 40 200100 400300 600 700 900 500 1000 1v range 2v range
ltc2242-10 2 224210fd a bsolu t e maxi m u m r a t ings supply voltage (v dd ) ............................................... 2.8 v digital output ground voltage (ognd) ........ C 0.3v to 1v analog input voltage (note 3) ...... C 0.3v to (v dd + 0.3v) digital input voltage ..................... C0.3v to (v dd + 0.3v) digital output voltage ................ C 0.3v to (ov dd + 0.3v) power dissipation ............................................. 15 00mw operating temperature range l tc2242c-10 ........................................... 0 c to 70c l tc2242i-10 ......................................... C 40c to 85c storage temperature range .................. C 65c to 150c ov dd = v dd (notes 1, 2) top view up package 64-lead (9mm 9mm) plastic qfn exposed pad (pin 65) is gnd, must be soldered to pcb t jmax = 150c, ja = 20c/w a in + 1 a in + 2 a in ? 3 a in ? 4 refha 5 refha 6 reflb 7 reflb 8 refhb 9 refhb 10 refla 11 refla 12 v dd 13 v dd 14 v dd 15 gnd 16 48 d7 + /da4 47 d7 ? /da3 46 d6 + /da2 45 d6 ? /da1 44 d5 + /da0 43 d5 ? /dnc 42 ov dd 41 ognd 40 d4 + /dnc 39 d4 ? /clkouta 38 d3 + /clkoutb 37 d3 ? /ofb 36 clkout + /db9 35 clkout ? /db8 34 ov dd 33 ognd 64 gnd 63 v dd 62 v dd 61 gnd 60 v cm 59 sense 58 mode 57 lvds 56 of + /ofa 55 of ? /da9 54 d9 + /da8 53 d9 ? /da7 52 d8 + /da6 51 d8 ? /da5 50 ognd 49 ov dd enc + 17 enc ? 18 shdn 19 oe 20 dnc 21 dnc 22 dnc/db0 23 dnc/db1 24 ognd 25 ov dd 26 d0 ? /db2 27 d0 + /db3 28 d1 ? /db4 29 d1 + /db5 30 d2 ? /db6 31 d2 + /db7 32 65 c onver t er c harac t eris t ics p in c on f igura t ion the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 4) parameter conditions min typ max units resolution (no missing codes) 10 bits integral linearity error differential analog input (note 5) C1 0.4 1 lsb differential linearity error differential analog input C0.7 0.2 0.7 lsb offset error (note 6) C17 5 17 mv gain error external reference C3.5 0.7 3.5 %fs lead free finish tape and reel part marking* package description temperature range LTC2242CUP-10#pbf LTC2242CUP-10#trpbf ltc2242up-10 64-lead (9mm 9mm) plastic qfn 0c to 70c ltc2242iup-10#pbf ltc2242iup-10#trpbf ltc2242up-10 64-lead (9mm 9mm) plastic qfn C40c to 85c lead based finish tape and reel part marking* package description temperature range LTC2242CUP-10#pbf LTC2242CUP-10#tr ltc2242up-10 64-lead (9mm 9mm) plastic qfn 0c to 70c ltc2242iup-10#pbf ltc2242iup-10#tr ltc2242up-10 64-lead (9mm 9mm) plastic qfn C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *temperature grades are identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ o r d er i n f or m a t ion ltc2242-10 3 224210fd a nalog i npu t the denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 4) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 2.375v < v dd < 2.625v (note 7) 0.5 to 1 v v in, cm analog input common mode (a in + + a in C )/2 differential input (note 7) 1.2 1.25 1.3 v i in analog input leakage current 0 < a in + , a in C < v dd C1 1 a i sense sense input leakage 0v < sense < 1v C1 1 a i mode mode pin pull-down current to gnd 7 a i lvds lvds pin pull-down current to gnd 7 a t ap sample and hold acquisition delay time 0.4 ns t jitter sample and hold acquisition delay time jitter 95 fs rms full power bandwidth figure 8 test circuit 1200 mhz dyna m ic a ccuracy the denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. a in = C1dbfs. (note 4) symbol parameter conditions min typ max units snr signal-to-noise ratio (note 10) 10mhz input 60.6 db 70mhz input l 59.2 60.5 db 140mhz input 60.5 db 240mhz input 60.4 db sfdr spurious free dynamic range 2nd or 3rd harmonic (note 11) 10mhz input 78 db 70mhz input l 63 75 db 140mhz input 74 db 240mhz input 73 db spurious free dynamic range 4th harmonic or higher (note 11) 10mhz input 85 db 70mhz input l 71 85 db 140mhz input 85 db 240mhz input 85 db s/(n+d) signal-to-noise plus distortion ratio (note 12) 10mhz input 60.4 db 70mhz input l 58.2 60.4 db 140mhz input 60.3 db 240mhz input 60.2 db imd intermodulation distortion f in1 = 135mhz, f in2 = 140mhz 81 dbc parameter conditions min typ max units offset drift 10 v/c full-scale drift internal reference external reference 60 45 ppm/c ppm/c transition noise sense = 1v 0.18 lsb rms conver t er charac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 4) ltc2242-10 4 224210fd i n t ernal r e f erence c harac t eris t ics (note 4) parameter conditions min typ max units v cm output voltage i out = 0 1.225 1.25 1.275 v v cm output tempco 35 ppm/c v cm line regulation 2.375v < v dd < 2.625v 3 mv/v v cm output resistance C1ma < i out < 1ma 2 digi t al i npu t s an d digi t al o u t pu t s the denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 4) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) v id differential input voltage (note 7) 0.2 v v icm common mode input voltage internally set externally set (note 7) 1.2 1.5 1.5 2.0 v v r in input resistance 4.8 k c in input capacitance (note 7) 2 pf logic inputs (oe, shdn) v ih high level input voltage v dd = 2.5v 1.7 v v il low level input voltage v dd = 2.5v 0.7 v i in input current v in = 0v to v dd C10 10 a c in input capacitance (note 7) 3 pf logic outputs (cmos mode) ov dd = 2.5v c oz hi-z output capacitance oe = high (note 7) 3 pf i source output source current v out = 0v 37 ma i sink output sink current v out = 2.5v 23 ma v oh high level output voltage i o = C10a i o = C500a 2.495 2.45 v v v ol low level output voltage i o = 10a i o = 500a 0.005 0.07 v v ov dd = 1.8v v oh high level output voltage i o = C500a 1.75 v v ol low level output voltage i o = 500a 0.07 v logic outputs (lvds mode) v od differential output voltage 100 differential load 247 350 454 mv v os output common mode voltage 100 differential load 1.125 1.250 1.375 v ltc2242-10 5 224210fd p ower r equire m en t s symbol parameter conditions min typ max units v dd analog supply voltage (note 8) 2.375 2.5 2.625 v p sleep sleep mode power shdn = high, oe = high, no clk 1 mw p nap nap mode power shdn = high, oe = low, no clk 28 mw lvds output mode ov dd output supply voltage (note 8) 2.375 2.5 2.625 v i vdd analog supply current 285 320 ma i ovdd output supply current 58 70 ma p diss power dissipation 858 975 mw cmos output mode ov dd output supply voltage (note 8) 0.5 2.5 2.625 v i vdd analog supply current (note 7) 285 320 ma p diss power dissipation 740 mw the denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 9) ti m ing c harac t eris t ics the denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 4) symbol parameter conditions min typ max units f s sampling frequency (note 8) 1 250 mhz t l enc low time (note 7) duty cycle stabilizer off duty cycle stabilizer on 1.9 1.5 2 2 500 500 ns ns t h enc high time (note 7) duty cycle stabilizer off duty cycle stabilizer on 1.9 1.5 2 2 500 500 ns ns t ap sample-and-hold aperture delay 0.4 ns t oe output enable delay (note 7) 5 10 ns lvds output mode t d enc to data delay (note 7) 1 1.7 2.8 ns t c enc to clkout delay (note 7) 1 1.7 2.8 ns data to clkout skew (t c C t d ) (note 7) C0.6 0 0.6 ns rise time 0.5 ns fall time 0.5 ns pipeline latency 5 cycles cmos output mode t d enc to data delay (note 7) 1 1.7 2.8 ns t c enc to clkout delay (note 7) 1 1.7 2.8 ns data to clkout skew (t c C t d ) (note 7) C0.6 0 0.6 ns pipeline latency full rate cmos 5 cycles demuxed interleaved 5 cycles demuxed simultaneous 5 and 6 cycles ltc2242-10 6 224210fd e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: v dd = 2.5v, f sample = 250mhz, lvds outputs, differential enc + /enc C = 2v p-p sine wave, input range = 2v p-p with differential drive, unless otherwise noted. note 5: integral nonlinearity is defined as the deviation of a code from a best straight line fit to the transfer curve. the deviation is measured from the center of the quantization band. typical p er f or m ance c harac t eris t ics note 6: offset error is the offset voltage measured from C0.5 lsb when the output code flickers between 00 0000 0000 and 11 1111 1111 in 2s complement output mode. note 7: guaranteed by design, not subject to test. note 8: recommended operating conditions. note 9: v dd = 2.5v, f sample = 250mhz, differential enc + /enc C = 2v p-p sine wave, input range = 1v p-p with differential drive, output c load = 5pf. note 10: snr minimum and typical values are for lvds mode. typical values for cmos mode are typically 0.2db lower. note 11: sfdr minimum values are for lvds mode. typical values are for both lvds and cmos modes. note 12: sinad minimum and typical values are for lvds mode. typical values for cmos mode are typically 0.2db lower. integral nonlinearity differential nonlinearity 8192 point fft, f in = 5mhz, C1db, 2v range, lvds mode (t a = 25c unless otherwise noted, note 4) output code 0 ?1.0 inl (lsb) ?0.8 ?0.4 ?0.2 0 1.0 0.4 256 512 224210 g01 ?0.6 0.6 0.8 0.2 768 1024 output code 0 ?1.0 dnl (lsb) ?0.8 ?0.4 ?0.2 0 1.0 0.4 256 512 224210 g02 ?0.6 0.6 0.8 0.2 768 1024 frequency (mhz) 0 amplitude (db) ?80 ?20 ?10 0 20 40 8060 100 224210 g03 ?100 ?40 ?60 ?90 ?30 ?110 ?50 ?70 120 ltc2242-10 7 224210fd typical p er f or m ance c harac t eris t ics 8192 point fft, f in = 70mhz, C1db, 2v range, lvds mode 8192 point fft, f in = 140mhz, C1db, 2v range, lvds mode 8192 point fft, f in = 240mhz, C1db, 2v range, lvds mode 8192 point fft, f in = 500mhz, C1db, 1v range, lvds mode 8192 point fft, f in = 1ghz, C1db, 1v range, lvds mode 8192 point 2-tone fft, f in = 135mhz and 140mhz, C1db, 2v range, lvds mode snr vs input frequency, C1db, lvds mode sfdr (hd2 and hd3) vs input frequency, C1db, lvds mode sfdr (hd4+) vs input frequency, C1db, lvds mode (t a = 25c unless otherwise noted, note 4) frequency (mhz) 0 amplitude (db) ?80 ?20 ?10 0 20 40 8060 100 224210 g04 ?100 ?40 ?60 ?90 ?30 ?110 ?50 ?70 120 frequency (mhz) 0 amplitude (db) ?80 ?20 ?10 0 20 40 8060 100 224210 g05 ?100 ?40 ?60 ?90 ?30 ?110 ?50 ?70 120 frequency (mhz) 0 amplitude (db) ?80 ?20 ?10 0 20 40 8060 100 224210 g06 ?100 ?40 ?60 ?90 ?30 ?110 ?50 ?70 120 frequency (mhz) 0 amplitude (db) ?80 ?20 ?10 0 20 40 8060 100 224210 g07 ?100 ?40 ?60 ?90 ?30 ?110 ?50 ?70 120 frequency (mhz) 0 amplitude (db) ?80 ?20 ?10 0 20 40 8060 100 224210 g08 ?100 ?40 ?60 ?90 ?30 ?110 ?50 ?70 120 frequency (mhz) 0 amplitude (db) ?80 ?20 ?10 0 20 40 8060 100 224210 g09 ?100 ?40 ?60 ?90 ?30 ?110 ?50 ?70 120 input frequency (mhz) 0 55 snr (dbfs) 56 57 58 600 700 800 900 62 224210 g10 100 200 300 400 500 1000 59 60 61 1v range 2v range input frequency (mhz) 0 sfdr (dbfs) 70 80 85 800 224210 g11 60 50 65 75 55 45 40 200100 400300 600 700 900 500 1000 1v range 2v range input frequency (mhz) 0 60 sfdr (dbfs) 65 75 80 85 95 100 500 700 224210 g12 70 90 400 900 1000 200 300 600 800 1v range 2v range ltc2242-10 8 224210fd typical p er f or m ance c harac t eris t ics sfdr and snr vs sample rate, 2v range, f in = 30mhz, C1db, lvds mode sfdr vs input level, f in = 70mhz, 2v range snr vs sense, f in = 5mhz, C1db i vdd vs sample rate, 5mhz sine wave input, C1db i ovdd vs sample rate, 5mhz sine wave input, C1db (t a = 25c unless otherwise noted, note 4) sample rate (msps) 0 90 85 80 75 70 65 60 55 150 200 250 224210 g13 50 100 300 sfdr and snr (dbfs) sfdr snr input level (dbfs) ?50 0 sfdr (dbc and dfbs) 10 30 40 50 90 70 ?40 ?20 ?10 224210 g14 20 80 60 ?30 dbfs dbc 0 sense pin (v) 0.5 60.0 60.5 61.0 0.9 224210 g15 59.5 59.0 0.6 0.7 0.8 1 58.5 58.0 57.5 snr (dbfs) sample rate (msps) 0 i vdd (ma) 250 260 270 150 250 224210 g16 240 230 220 50 100 200 280 290 300 2v range 1v range sample rate (msps) 0 0 i ovdd (ma) 10 20 30 40 60 50 100 150 200 250 224210 g17 50 cmos outputs o vdd = 1.8v lvds outputs o vdd = 2.5v ltc2242-10 9 224210fd p in func t ions a in + (pins 1, 2): positive differential analog input. a in C (pins 3, 4): negative differential analog input. refha (pins 5, 6): adc high reference. bypass to pins 7, 8 with 0.1f ceramic chip capacitor, to pins 11, 12 with a 2.2f ceramic capacitor and to ground with 1f ceramic capacitor. reflb (pins 7, 8): adc low reference. bypass to pins 5, 6 with 0.1f ceramic chip capacitor. do not connect to pins 11, 12. refhb (pins 9, 10): adc high reference. bypass to pins 11, 12 with 0.1f ceramic chip capacitor. do not connect to pins 5, 6. refla (pins 11, 12): adc low reference. bypass to pins 9, 10 with 0.1f ceramic chip capacitor, to pins 5, 6 with a 2.2f ceramic capacitor and to ground with 1f ceramic capacitor. v dd (pins 13, 14, 15, 62, 63): 2.5v supply. bypass to gnd with 0.1f ceramic chip capacitors. gnd (pins 16, 61, 64): adc power ground. enc + (pin 17): encode input. conversion starts on the positive edge. enc C (pin 18): encode complement input. conversion starts on the negative edge. bypass to ground with 0.1f ceramic for single-ended encode signal. shdn (pin 19): shutdown mode selection pin. connecting shdn to gnd and oe to gnd results in normal operation with the outputs enabled. connecting shdn to gnd and oe to v dd results in normal operation with the outputs at high impedance. connecting shdn to v dd and oe to gnd results in nap mode with the outputs at high impedance. connecting shdn to v dd and oe to v dd results in sleep mode with the outputs at high impedance. oe (pin 20): output enable pin. refer to shdn pin function. dnc (pins 21, 22, 40, 43): do not connect these pins. db0-db9 (pins 23, 24, 27, 28, 29, 30, 31, 32, 35, 36): digital outputs, b bus. db9 is the msb. at high impedance in full rate cmos mode. ognd (pins 25, 33, 41, 50): output driver ground. ov dd (pins 26, 34, 42, 49): positive supply for the output drivers. bypass to ground with 0.1f ceramic chip capacitor. ofb (pin 37): over/under flow output for b bus. high when an over or under flow has occurred. at high imped- ance in full rate cmos mode. clkoutb (pin 38): data valid output for b bus. in demux mode with interleaved update, latch b bus data on the fall- ing edge of clkoutb. in demux mode with simultaneous update, latch b bus data on the rising edge of clkoutb. this pin does not become high impedance in full rate cmos mode. clkouta (pin 39): data valid output for a bus. latch a bus data on the falling edge of clkouta. da0-da9 (pins 44, 45, 46, 47, 48, 51, 52, 53, 54, 55): digital outputs, a bus. da9 is the msb. ofa (pin 56): over/under flow output for a bus. high when an over or under flow has occurred. lvds (pin 57): output mode selection pin. connecting lvds to 0v selects full rate cmos mode. connecting lvds to 1/3v dd selects demux cmos mode with simultaneous update. connecting lvds to 2/3v dd selects demux cmos mode with interleaved update. connecting lvds to v dd selects lvds mode. mode (pin 58): output format and clock duty cycle stabilizer selection pin. connecting mode to 0v selects offset binary output format and turns the clock duty cycle stabilizer off. connecting mode to 1/3v dd selects offset binary output format and turns the clock duty cycle st abilizer on. connecting mode to 2/3v dd selects 2s complement output format and turns the clock duty cycle stabilizer on. connecting mode to v dd selects 2s complement output format and turns the clock duty cycle stabilizer off. sense (pin 59): reference programming pin. connecting sense to v cm selects the internal reference and a 0.5v input range. connecting sense to v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to sense selects an input range of v sense . 1v is the largest valid input range. v cm (pin 60): 1.25v output and input common mode bias. bypass to ground with 2.2f ceramic chip capacitor. gnd (exposed pad) (pin 65): adc power ground. the exposed pad on the bottom of the package needs to be soldered to ground. (cmos mode) ltc2242-10 10 224210fd pin f unc t ions ain + (pins 1, 2): positive differential analog input. ain C (pins 3, 4): negative differential analog input. refha (pins 5, 6): adc high reference. bypass to pins 7, 8 with 0.1f ceramic chip capacitor, to pins 11, 12 with a 2.2f ceramic capacitor and to ground with 1f ceramic capacitor. reflb (pins 7, 8): adc low reference. bypass to pins 5, 6 with 0.1f ceramic chip capacitor. do not connect to pins 11, 12. refhb (pins 9, 10): adc high reference. bypass to pins 11, 12 with 0.1f ceramic chip capacitor. do not connect to pins 5, 6. refla (pins 11, 12): adc low reference. bypass to pins 9, 10 with 0.1f ceramic chip capacitor, to pins 5, 6 with a 2.2f ceramic capacitor and to ground with 1f ceramic capacitor. v dd (pins 13, 14, 15, 62, 63): 2.5v supply. bypass to gnd with 0.1f ceramic chip capacitors. gnd (pins 16, 61, 64): adc power ground. enc + (pin 17): encode input. conversion starts on the positive edge. enc C (pin 18): encode complement input. conversion starts on the negative edge. bypass to ground with 0.1f ceramic for single-ended encode signal. shdn (pin 19): shutdown mode selection pin. connecting shdn to gnd and oe to gnd results in normal operation with the outputs enabled. connecting shdn to gnd and oe to v dd results in normal operation with the outputs at high impedance. connecting shdn to v dd and oe to gnd results in nap mode with the outputs at high impedance. connecting shdn to v dd and oe to v dd results in sleep mode with the outputs at high impedance. oe (pin 20): output enable pin. refer to shdn pin function. dnc (pins 21, 22, 23, 24): do not connect these pins. d0 C /d0 + to d9 C /d9 + (pins 27, 28, 29, 30, 31, 32, 37, 38, 39, 40, 43, 44, 45, 46, 47, 48, 51, 52, 53, 54): lvds digital outputs. all lvds outputs require differential 100 termination resistors at the lvds receiver. d9 C /d9 + is the msb. ognd (pins 25, 33, 41, 50): output driver ground. ov dd (pins 26, 34, 42, 49): positive supply for the out- put drivers. bypass to ground with 0.1f ceramic chip capacitor. clkout C /clkout + (pins 35 to 36): lvds data valid output. latch data on rising edge of clkout C , falling edge of clkout + . of C /of + (pins 55 to 56): lvds over/under flow output. high when an over or under flow has occurred. lvds (pin 57): output mode selection pin. connecting lvds to 0v selects full rate cmos mode. connecting lvds to 1/3v dd selects demux cmos mode with simultaneous update. connecting lvds to 2/3v dd selects demux cmos mode with interleaved update. connecting lvds to v dd selects lvds mode. mode (pin 58): output format and clock duty cycle stabilizer selection pin. connecting mode to 0v selects offset binary output format and turns the clock duty cycle stabilizer off. connecting mode to 1/3v dd selects offset binary output format and turns the clock duty cycle st abilizer on. connecting mode to 2/3v dd selects 2s complement output format and turns the clock duty cycle stabilizer on. connecting mode to v dd selects 2s complement output format and turns the clock duty cycle stabilizer off. sense (pin 59): reference programming pin. connecting sense to v cm selects the internal reference and a 0.5v input range. connecting sense to v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to sense selects an input range of v sense . 1v is the largest valid input range. v cm (pin 60): 1.25v output and input common mode bias. bypass to ground with 2.2f ceramic chip capacitor. gnd (exposed pad) (pin 65): adc power ground. the exposed pad on the bottom of the package needs to be soldered to ground. (lvds mode) ltc2242-10 11 224210fd func t ional b lock diagra m figure 1. functional block diagram diff ref amp ref buf 2.2f 1f 0.1f 0.1f 1f internal clock signals refh refl differential input low jitter clock driver range select 1.25v reference first pipelined adc stage fifth pipelined adc stage fourth pipelined adc stage second pipelined adc stage enc + refha reflb refla refhb enc ? shift register and correction oe m0de ognd of ov dd d9 d0 clkout 224210 f01 input s/h sense v cm a in ? a in + 2.2f third pipelined adc stage output drivers control logic lvds shdn ? ? ? + ? + ? + ? + ? v dd gnd ltc2242-10 12 224210fd ti m ing diagra m s lvds output mode timing all outputs are differential and have lvds levels full-rate cmos output mode timing all outputs are single-ended and have cmos levels t h t d t c t l n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 t ap n + 1 n + 2 n + 4 n + 3 n analog input enc ? enc + clkout ? clkout + d0-d9, of 224210 td01 t ap n + 1 n + 2 n + 4 n + 3 n analog input t h t d t c t l n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 enc ? enc + clkoutb clkouta da0-da9, ofa db0-db9, ofb 224210 td02 high impedance ltc2242-10 13 224210fd t i m ing d iagra m s demultiplexed cmos outputs with interleaved update all outputs are single-ended and have cmos levels demultiplexed cmos outputs with simultaneous update all outputs are single-ended and have cmos levels t h t d t c t c t d t l n ? 5 n ? 3 n ? 1 n ? 6 n ? 4 n ? 2 enc ? enc + clkoutb clkouta da0-da9, ofa db0-db9, ofb 224210 td03 t ap n + 1 n + 2 n + 4 n + 3 n analog input t h t d t c t d t l n ? 6 n ? 4 n ? 2 n ? 5 n ? 3 n ? 1 enc ? enc + clkoutb clkouta da0-da9, ofa db0-db9, ofb 224210 td04 t ap n + 1 n + 2 n + 4 n + 3 n analog input ltc2242-10 14 224210fd a pplica t ions i n f or m a t ion dynamic performance signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n + d)] is the ratio between the rms amplitude of the fundamen- tal input frequency and the rms amplitude of all other frequency components at the adc output. the output is band limited to frequencies above dc to below half the sampling frequency. signal-to-noise ratio the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = 20log v2 2 + v3 2 + v4 2 + ...vn 2 ( ) / v1 ? ? ? ? ? ? where v1 is the rms amplitude of the fundamental fre- quency and v2 through vn are the amplitudes of the second through nth harmonics. the thd calculated in this data sheet uses all the harmonics up to the fifth. intermodulation distortion if the adc input signal consists of more than one spectral component, the adc transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are ap- plied to the adc input, nonlinearities in the adc transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. the 3rd order intermodulation products are 2fa + fb, 2fb + fa, 2fa C fb and 2fb C fa. the intermodula- tion distortion is defined as the ratio of the rms value of either input tone to the rms value of the largest 3rd order intermodulation product. spurious free dynamic range (sfdr) spurious free dynamic range is the peak harmonic or spuri- ous noise that is the largest spectral component excluding the input signal and dc. this value is expressed in decibels relative to the rms value of a full scale input signal. full power bandwidth the full power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full scale input signal. aperture delay time the time from when a rising enc + equals the enc C voltage to the instant that the input signal is held by the sample and hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C20log (2 ? f in ? t jitter ) converter operation as shown in figure 1, the ltc2242-10 is a cmos pipelined multi-step converter. the converter has five pipelined adc stages; a sampled analog input will result in a digitized value five cycles later (see the timing diagram section). for optimal performance the analog inputs should be driven differentially. the encode input is differential for improved common mode noise immunity. the ltc2242 - 10 has two phases of operation, determined by the state of the dif- ferential enc + /enc C input pins. for brevity, the text will refer to enc + greater than enc C as enc high and enc + less than enc C as enc low. ltc2242-10 15 224210fd a pplica t ions i n f or m a t ion each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage residue amplifier. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is amplified and output by the residue amplifier. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and vice versa. when enc is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that enc transitions from low to high, the sampled input is held. while enc is high, the held input voltage is buffered by the s/h amplifier which drives the first pipelined adc stage. the first stage acquires the output of the s/h dur - ing this high phase of enc. when enc goes back low, the first stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when enc goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the fifth stage adc for final evaluation. each adc stage following the first has additional range to accommodate flash and amplifier offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. sample/hold operation and input drive sample/hold operation figure 2 shows an equivalent circuit for the ltc2242-10 cmos differential sample-and-hold. the analog inputs are connected to the sampling capacitors (c sample ) through nmos transistors. the capacitors shown attached to each input (c parasitic ) are the summation of all other capacitance associated with each input. during the sample phase when enc is low, the transistors connect the analog inputs to the sampling capacitors and they charge to, and track the differential input voltage. when enc transitions from low to high, the sampled input voltage is held on the sampling capacitors. during the hold phase when enc is high, the sampling capacitors are disconnected from the input and the held voltage is passed to the adc core for processing. as enc transitions from high to low, the inputs are reconnected to the sampling capacitors to acquire a new sample. since the sampling capacitors still hold the previous sample, a charging glitch proportional to the change in voltage between samples will be seen at this time. if the change between the last sample and the new sample is small, the charging glitch seen at the input will be small. if the input change is large, such as the change seen with input frequencies near nyquist, then a larger charging glitch will be seen. common mode bias for optimal performance the analog inputs should be driven differentially. each input should swing 0.5v for the 2v range or 0.25v for the 1v range, around a common mode voltage of 1.25v. the v cm output pin (pin 60) may be used to provide the common mode bias level. v cm can be tied directly to the center tap of a transformer to set the dc input level or as a reference level to an op amp c sample 2pf r on 14 r on 14 v dd v dd ltc2242-10 a in + 224210 f02 c sample 2pf v dd a in ? enc ? enc + 1.5v 6k 1.5v 6k c parasitic 1.8pf c parasitic 1.8pf 10 10 figure 2. equivalent input circuit ltc2242-10 16 224210fd applica t ions in f or m a t ion differential driver circuit. the v cm pin must be bypassed to ground close to the adc with a 2.2f or greater capacitor. input drive impedance as with all high performance, high speed adcs, the dy - namic performance of the ltc2242-10 can be influenced by the input drive circuitry, particularly the second and third harmonics. source impedance and input reactance can influence sfdr. at the falling edge of enc, the sample- and-hold circuit will connect the 2pf sampling capacitor to the input pin and start the sampling period. the sampling period ends when enc rises, holding the sampled input on the sampling capacitor. ideally the input circuitry should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2f s ); however, this is not always possible and the incomplete settling may degrade the sfdr. the sampling glitch has been designed to be as linear as possible to minimize the effects of incomplete settling. for the best performance, it is recommended to have a source impedance of 100 or less for each input. the source impedance should be matched for the differential inputs. poor matching will result in higher even order harmonics, especially the second. input drive circuits figure 3 shows the ltc2242-10 being driven by an rf transformer with a center tapped secondary. the secondary center tap is dc biased with v cm , setting the adc input signal at its optimum dc level. terminating on the trans - former secondary is desirable, as this provides a common mode path for charging glitches caused by the sample and hold. figure 3 shows a 1:1 turns ratio transformer. other turns ratios can be used if the source impedance seen by the adc does not exceed 100 for each adc input. a disadvantage of using a transformer is the loss of low frequency response. most small rf transformers have poor performance at frequencies below 1mhz. figure 4 demonstrates the use of a differential amplifier to convert a single ended input signal into a differential input signal. the advantage of this method is that it provides low frequency input response; however, the limited gain bandwidth of most op amps will limit the sfdr at high input frequencies. figure 5 shows a capacitively-coupled input circuit. the impedance seen by the analog inputs should be matched. the 25 resistors and 12pf capacitor on the analog inputs serve two purposes: isolating the drive circuitry from figure 3. single-ended to differential conversion using a transformer figure 4. differential drive with an amplifier figure 5. capacitively-coupled drive 25 25 25 25 10 0.1f a in + a in + a in ? a in ? 12pf 2.2f v cm ltc2242-10 analog input 0.1 f t1 1:1 t1 = ma/com etc1-1t resistors, capacitors are 0402 package size 224210 f03 25 25 50 a in + a in + a in ? a in ? 12pf 2.2f 3pf v cm ltc2242-10 224210 f04 ? ? + + cm analog input high speed differential amplifier 3pf 0.1f 25 0.1f v cm a in + a in + a in ? a in ? 100 100 analog input 12pf 224210 f05 2.2f 0.1f 25 ltc2242-10 ltc2242-10 17 224210fd a pplica t ions i n f or m a t ion the sample-and-hold charging glitches and limiting the wideband noise at the converter input. for input frequen- cies higher than 100mhz, the capacitor may need to be decreased to prevent excessive signal loss. the a in + and a in C inputs each have two pins to reduce package inductance. the two a in + and the two a in C pins should be shorted together. for input frequencies above 100mhz the input circuits of figure 6, 7 and 8 are recommended. the balun transformer gives better high frequency response than a flux coupled center tapped transformer. the coupling capacitors allow the analog inputs to be dc biased at 1.25v. in figure 8 the series inductors are impedance matching elements that maximize the adc bandwidth. reference operation figure 9 shows the ltc2242-10 reference circuitry consist - ing of a 1.25v bandgap reference, a difference amplifier and switching and control circuit. the internal voltage reference can be configured for two pin selectable input ranges of 2v (1v differential) or 1v (0.5v differential). tying the sense pin to v dd selects the 2v range; typing the sense pin to v cm selects the 1v range. the 1.25v bandgap reference serves two functions: its output provides a dc bias point for setting the common mode voltage of any external input circuitry; additionally, the reference is used with a difference amplifier to gener - ate the differential reference levels needed by the internal adc circuitry. an external bypass capacitor is required for the 1.25v reference output, v cm . this provides a high frequency low impedance path to ground for internal and external circuitry. the difference amplifier generates the high and low reference for the adc. high speed switching circuits are connected to these outputs and they must be externally bypassed. each output has four pins: two each of refha and refhb for the high reference and two each of refla and reflb for the low reference. the multiple output pins are needed to reduce package inductance. bypass capaci - tors must be connected as shown in figure 9. figure 6. recommended front end circuit for input frequencies between 100mhz and 250mhz figure 7. recommended front end circuit for input frequencies between 250mhz and 500mhz figure 8. recommended front end circuit for input frequencies above 500mhz 25 25 12 12 10 0.1f a in + a in + a in ? a in ? 8pf 2.2f v cm analog input 0.1f 0.1f t1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size 224210 f06 ltc2242-10 25 10 25 0.1f a in + a in + a in ? a in ? 2.2f v cm analog input 0.1f 0.1f t1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size 224210 f07 ltc2242-10 25 10 25 0.1f a in + a in + a in ? a in ? 2.2f v cm ltc2242-10 analog input 0.1f 0.1f t1 t1 = ma/com etc1-1-13 resistors, capacitors are 0402 package size 224210 f08 2.7nh 2.7nh ltc2242-10 18 224210fd applica t ions in f or m a t ion other voltage ranges in between the pin selectable ranges can be programmed with two external resistors as shown in figure 10. an external reference can be used by ap- plying its output directly or through a resistor divider to sense. it is not recommended to drive the sense pin with a logic device. the sense pin should be tied to the appropriate level as close to the converter as possible. if the sense pin is driven externally, it should be bypassed to ground as close to the device as possible with a 1f ceramic capacitor. input range the input range can be set based on the application. the 2v input range will provide the best signal-to-noise performance while maintaining excellent sfdr. the 1v input range will have better sfdr performance, but the snr will degrade by 1.7db. see the typical performance characteristics section. driving the encode inputs the noise performance of the ltc2242-10 can depend on the encode signal quality as much as on the analog input. the enc + /enc C inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. each input is biased through a 4.8k resistor to a 1.5v bias. the bias resistors set the dc op- erating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. any noise present on the encode signal will result in ad- ditional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical (high input frequen - cies) take the following into consideration: 1. differential drive should be used. 2. use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. if the adc is clocked with a sinusoidal signal, filter the encode signal to reduce wideband noise. 4. balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. the encode inputs have a common mode range of 1.2v to 2.0v. each input may be driven from ground to v dd for single-ended drive. figure 9. equivalent reference circuit figure 10. 1.5v range adc v cm refha reflb sense tie to v dd for 2v range; tie to v cm for 1v range; range = 2 ? v sense for 0.5v < v sense < 1v 1.25v refla refhb 2.2f 2.2f internal adc high reference buffer 0.1f 224210 f09 ltc2242 -10 2 diff amp 1f 1f 0.1f internal adc low reference 1.25v bandgap reference 1v 0.5v range detect and control v cm sense 1.25v 2.2f 8k 12k 0.75v 1f 224210 f10 ltc2242-10 ltc2242-10 19 224210fd a pplica t ions i n f or m a t ion maximum and minimum encode rates the maximum encode rate for the ltc2242-10 is 250msps. for the adc to operate properly, the encode signal should have a 50% (5%) duty cycle. each half cycle must have at least 1.9ns for the adc internal circuitry to have enough settling time for proper operation. achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as pecl or lvds. an optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. this circuit uses the rising edge of the enc + pin to sample the analog input. the falling edge of enc + is ignored and the internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin should be connected to 1/3v dd or 2/3v dd using external resistors. the lower limit of the ltc2242-10 sample rate is determined by droop of the sample-and-hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the specified minimum operating frequency for the ltc2242-10 is 1msps. digital outputs table 1 shows the relationship between the analog input voltage, the digital data bits, and the overflow bit. figure 11. transformer driven enc + /enc C figure 12a. single-ended enc drive, not recommended for low jitter figure 12b. enc drive using lvds v dd v dd ltc2242-10 224210 f11 v dd enc ? enc + 1.5v bias 1.5v bias 0.1f t1 ma/com etc1-1-13 clock input 100 8.2pf 0.1f 0.1f 50 ?? 50 4.8k 4.8k to internal adc circuits 224210 f12a enc ? 1.5v v threshold = 1.5v enc + 0.1f ltc2242-10 224210 f12b enc ? enc + lvds clock 100 0.1f ltc2242-10 0.1f ltc2242-10 20 224210fd applica t ions in f or m a t ion table 1. output codes vs input voltage a in + C a in C (2v range) of d9 C d0 (offset binary) d9 C d0 (2s complement) >+1.000000v +0.998047v +0.996094v 1 0 0 11 1111 1111 11 1111 1111 11 1111 1110 01 1111 1111 01 1111 1111 01 1111 1110 +0.001953v 0.000000v C0.001953v C0.003906v 0 0 0 0 10 0000 0001 10 0000 0000 01 1111 1111 01 1111 1110 00 0000 0001 00 0000 0000 11 1111 1111 11 1111 1110 C0.998047v C1.000000v ltc2242-10 22 224210fd applica t ions in f or m a t ion output enable the outputs may be disabled with the output enable pin, oe . in cmos or lvds output modes oe high disables all data outputs including of and clkout. the data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. the output hi-z state is intended for use during long periods of inactivity. the hi-z state is not a truly open circuit; the output pins that make an lvds output pair have a 20k resistance be - tween them. therefore in the cmos output mode, adjacent data bits will have 20k resistance in between them, even in the hi-z state. sleep and nap modes the converter may be placed in shutdown or nap modes to conserve power. connecting shdn to gnd results in normal operation. connecting shdn to v dd and oe to v dd results in sleep mode, which powers down all circuitry including the reference and typically dissipates 1mw. when exiting sleep mode it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. connecting shdn to v dd and oe to gnd results in nap mode, which typically dis- sipates 28mw. in nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. in both sleep and nap mode all digital outputs are disabled and enter the hi-z state. grounding and bypassing the ltc2242-10 requires a printed circuit board with a clean unbroken ground plane. a multilayer board with an internal ground plane is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital signal alongside an analog signal or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm , refha, refhb, refla and reflb pins. bypass capacitors must be located as close to the pins as possible. of particular importance are the capaci - tors between refha and reflb and between refhb and refla. these capacitors should be as close to the device as possible (1.5mm or less). size 0402 ceramic capacitors are recommended. the 2.2f capacitor between refha and refla can be somewhat further away. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the ltc2242-10 differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the ltc2242-10 is trans - ferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance, the exposed pad should be soldered to a large grounded pad on the pc board. it is critical that all ground pins are connected to a ground plane of sufficient area. clock sources for undersampling undersampling is especially demanding on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. a clock source that degrades snr of a full-scale signal by 1db at 70mhz will degrade snr by 3db at 140mhz, and 4.5db at 190mhz. in cases where absolute clock frequency accuracy is relatively unimportant and only a single adc is required, a canned oscillator from vendors such as saronix or vectron can be placed close to the adc and simply con - nected directly to the adc. if there is any distance to the adc, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. you must not allow the clock to overshoot the supplies or performance will suffer. do not filter the clock signal with a narrow band filter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise. ltc2242-10 23 224210fd a pplica t ions i n f or m a t ion the lowest phase noise oscillators have single-ended si- nusoidal outputs, and for these devices the use of a filter close to the adc may be beneficial. this filter should be close to the adc to both reduce roundtrip reflection times, as well as reduce the susceptibility of the traces between the filter and the adc. if the circuit is sensitive to close- in phase noise, the power supply for oscillators and any buffers must be very stable, or propagation delay variation with supply will translate into phase noise. even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. if your clock is also used to drive digital devices such as an fpga, you should locate the oscillator, and any clock fan-out devices close to the adc, and give the routing to the adc prece- dence. the clock signals to the fpga should have series termination at the driver to prevent high frequency noise from the fpga disturbing the substrate of the clock fan-out device. if you use an fpga as a programmable divider, you must re-time the signal using the original oscillator, and the re-timing flip-flop as well as the oscillator should be close to the adc, and powered with a very quiet supply. for cases where there are multiple adcs, or where the clock source originates some distance away, differential clock distribution is advisable. this is advisable both from the perspective of emi, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multilayer pcbs. the differential pairs must be close together and distanced from other signals. the differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart. ltc2242-10 24 224210fd applica t ions in f or m a t ion evaluation circuit schematic of the ltc2242-10 a in + a in + a in ? a in ? refha refha reflb reflb refhb refhb refla refla c19 0.1f 2 1 4 3 6 5 8 7 10 9 12 11 56 55 54 53 52 51 48 47 46 45 44 43 40 39 38 37 36 35 32 31 30 29 28 27 24 23 22 21 r17 100? r3 100? r7 1k r37 blm18bb470sn1d r38 100? r39 100? r40 100? r42 100? r43 100? r18 100? r19 100? r20 100? r21 100? r22 100? r28 100? r30 100? 24 of + /ofa of ? /da9 d9 + /da8 d9 ? /da7 d8 + /da6 d8 ? /da5 d7 + /da4 d7 ? /da3 d6 + /da2 d6 ? /da1 d5 + /da0 d5 ? /dnc d4 + /dnc d4 ? /clkouta d3 + /clkoutb d3 ? /ofb clkout + /db9 clkout ? /db8 d2 + /db7 d2 ? /db6 d1 + /db5 d1 ? /db4 d0 + /db3 d0 ? /db2 dnc/db1 dnc/db0 dnc dnc ltc2242-10 gnd gnd gnd gnd v dd v dd v dd v dd v dd 65 64 61 16 63 62 15 14 13 c26 0.1 f c25 0.1 f 2.5v ov dd ov dd ov dd ov dd ognd ognd ognd ognd 25 33 41 50 26 34 42 49 tp6 v cm enc+ enc? shdn oe sense mode lvds v cm c20 0.1f c21 0.1f c23 0.1f c22 0.1f tp1 ext ref tp2 gnd shdn 3 v dd 1 gnd 5 4 oe 2 v dd 6 gnd 2.5v 1 v cm 3 ext ref 5 2 4 6 17 18 60 19 20 59 58 57 2.5v 2.5v 2.5v r24 1k j4 sense 1 v dd 3 gnd 5 2 4 2/3 6 1/3 j2 mode r6 1k r8 1k lt1763cde-2.5 in in shdn v o v o 10 11 8 sen 2 21 3 5 6 byp gnd gp gp 7 c38 0.01f c34 0.1f c36 4.7f j6 aux pwr connector c24 10f +2.5v +3.3v 3.3v tp5 gnd tp4 2.5v tp3 (no turret) 1 2 3 en12 en34 en56 en78 en i 1n i 1p i 2n i 2p i 3n i 3p i 4n i 4p i 5n i 5p i 6n i 6p i 7n i 7p i 8n i 8p v bb o 1n o 1p o 2n o 2p o 3n o 3p o 4n o 4p o 5n o 5p o 6n o 6p o 7n o 7p o 8n o 8p v c1 v c2 v c3 v c4 v c5 12 25 26 47 48 v e1 v e2 v e3 v e4 v e5 1 2 23 36 37 u3 finii08 3.3v en12 en34 en56 en78 en i 1n i 1p i 2n i 2p i 3n i 3p i 4n i 4p i 5n i 5p i 6n i 6p i 7n i 7p i 8n i 8p v bb o 1n o 1p o 2n o 2p o 3n o 3p o 4n o 4p o 5n o 5p o 6n o 6p o 7n o 7p o 8n o 8p v c1 v c2 v c3 v c4 v c5 12 25 26 47 48 v e1 v e2 v e3 v e4 v e5 1 2 23 36 37 u3 finii08 3.3v 3 22 27 46 13 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 45 44 43 42 41 40 39 38 35 34 33 32 31 30 29 28 45 44 43 42 41 40 39 38 35 34 33 32 31 30 29 28 3 22 27 46 13 4 5 6 7 8 9 10 11 14 15 16 17 18 19 20 21 24 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 lvds buffer bypass c28 0.1f c29 0.1f 3.3v c30 0.1f c31 0.1f c32 0.1f c33 0.1f c5 0.1f c8 0.1f r16 100k v cc 24lc02st gnd 4 224210 ai01 8 array eeprom scl sda wp a2 a1 a0 6 5 7 3 2 1 c27 0.1f r46 4990? r29 4990? 2.5v r26 4990? r1 49.9? r2 49.9? r4 4.99? r5 4.99? j7 encode clk c3 0.1f c11 0.1f c4 1.8pf r41 100? c13 0.1f c14 0.1f c15 1f c16 1f c17 2.2f r23 100? c12 0.1f c9 1.8pf r11 49.9? r12 49.9? r13 4.99? r14 4.99? r9 12.4? r10 12.4? c18 2.2f c10 0.1f r15 49.9? t2 maba-007159-000000 r27 49.9? a in c6 0.1f j5 sma c2 0.1f c7 0.1f sma c1 0.1f t1 maba-007159-000000 version device bits sample rate dc997b-a ltc2242-12 12 250msps dc997b-b ltc2241-12 12 210msps dc997b-c ltc2240-12 12 170msps dc997b-d ltc2242-10 10 250msps dc997b-e ltc2241-10 10 210msps dc997b-f ltc2240-10 10 170msps r25 1k u5 sj ltc2242-10 25 224210fd a pplica t ions i n f or m a t ion silkscreen top layer 2 gnd plane layer 1 component side ltc2242-10 26 224210fd applica t ions in f or m a t ion layer 4 power/ground planes layer 5 power/ground planes layer 3 power/ground plane ltc2242-10 27 224210fd applica t ions in f or m a t ion layer back solder side silk screen back, solder side ltc2242-10 28 224210fd 9 .00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation wnjr-5 2. all dimensions are in millimeters 3. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 4. exposed pad shall be solder plated 5. shaded area is only a reference for pin 1 location on the top and bottom of package 6. drawing not to scale pin 1 top mark (see note 5) 0.40 0.10 6463 1 2 bottom view?exposed pad 7.15 0.10 7.15 0.10 7.50 ref (4-sides) 0.75 0.05 r = 0.10 typ r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (up64) qfn 0406 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 7.50 ref (4 sides) 7.15 0.05 7.15 0.05 8.10 0.05 9.50 0.05 0.25 0.05 0.50 bsc package outline pin 1 chamfer c = 0.35 p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. up package 64-lead plastic qfn (9mm 9mm) (reference ltc dwg # 05-08-1705 rev c) ltc2242-10 29 224210fd information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number d 10/11 corrected part number on schematic drawing in applications information. reordered board layers in applications information. 24 25 - 27 (revision history begins at rev d) ltc2242-10 30 224210fd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 1011 rev d ? printed in usa r ela t e d p ar t s part number description comments ltc1748 14-bit, 80msps, 5v adc 76.3db snr, 90db sfdr, 48-pin tssop ltc1750 14-bit, 80msps, 5v wideband adc up to 500mhz if undersampling, 90db sfdr lt ? 1993-2 high speed differential op amp 800mhz bw, 70dbc distortion at 70mhz, 6db gain lt1994 low noise, low distortion fully differential input/output amplifier/driver low distortion: C94dbc at 1mhz ltc2202 16-bit, 10msps, 3.3v adc, lowest noise 150mw, 81.6db snr, 100db sfdr, 48-pin qfn ltc2208 16-bit, 130msps, 3.3v adc, lvds outputs 1250mw, 78db snr, 100db sfdr, 48-pin qfn ltc2220 12-bit, 170msps, 3.3v adc, lvds outputs 890mw, 67.7db snr, 84db sfdr, 64-pin qfn ltc2220-1 12-bit, 185msps, 3.3v adc, lvds outputs 910mw, 67.7db snr, 80db sfdr, 64-pin qfn ltc2221 12-bit, 135msps, 3.3v adc, lvds outputs 660mw, 67.8db snr, 84db sfdr, 64-pin qfn ltc2224 12-bit, 135msps, 3.3v adc, high if sampling 630mw, 67.6db snr, 84db sfdr, 48-pin qfn ltc2230 10-bit, 170msps, 3.3v adc, lvds outputs 890mw, 61.2db snr, 78db sfdr, 64-pin qfn ltc2231 10-bit, 135msps, 3.3v adc, lvds outputs 660mw, 61.2db snr, 78db sfdr, 64-pin qfn ltc2240-10 10-bit, 170msps, 2.5v adc, lvds outputs 445mw, 60.6db snr, 78db sfdr, 64-pin qfn ltc2240-12 12-bit, 170msps, 2.5v adc, lvds outputs 445mw, 65.5db snr, 78db sfdr, 64-pin qfn ltc2241-10 10-bit, 210msps, 2.5v adc, lvds outputs 585mw, 60.6db snr, 78db sfdr, 64-pin qfn ltc2242-12 12-bit, 210msps, 2.5v adc, lvds outputs 585mw, 65.5db snr, 78db sfdr, 64-pin qfn ltc2242-12 12-bit, 250msps, 2.5v adc, lvds outputs 740mw, 65.5db snr, 78db sfdr, 64-pin qfn ltc2255 14-bit, 125msps, 3v adc, lowest power 395mw, 72.5db snr, 88db sfdr, 32-pin qfn ltc2284 14-bit, dual, 105msps, 3v adc, low crosstalk 540mw, 72.4db snr, 88db sfdr, 64-pin qfn lt5512 dc to 3ghz high signal level downconverting mixer dc to 3ghz, 21dbm iip3, integrated lo buffer lt5514 ultralow distortion if amplifier/adc driver with digitally controlled gain 450mhz to 1db bw, 47db oip3, digital gain control 10.5db to 33db in 1.5db/step lt5515 1.5ghz to 2.5ghz direct conversion quadrature demodulator high iip3: 20dbm at 1.9ghz, integrated lo quadrature generator lt5516 800mhz to 1.5ghz direct conversion quadrature demodulator high iip3: 21.5dbm at 900mhz, integrated lo quadrature generator lt5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator lt5522 600mhz to 2.7ghz high linearity downconverting mixer 4.5v to 5.25v supply, 25dbm iip3 at 900mhz, nf = 12.5db, 50 single-ended rf and lo ports |
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